1. Field of the Invention
This invention generally relates to analog-to-digital signal conversion and, more particularly, to a system and method for correcting phase errors in a synthesized frequency multiplier clock signal.
2. Description of the Related Art
FIG. 1 depicts a phase-locked loop (PLL) consisting of a phase frequency detector (PFD), a voltage controlled oscillator (VCO), a charge pump (CP), and a loop filter placed into the forward path of a negative feedback closed loop configuration (prior art). The charge pump converts the pulse width modulated output voltage of the PFD into current pulses. The amplitude of the current is often made to track some static or almost static parameter such as the manufacturing process, temperature, and supply voltage. It can also be varied with the output frequency of the PLL. The VCO runs at the desired output clock frequency, or some multiple of it. Due to fundamental limitations the VCO itself is not inherently accurate or stable. To obtain a stable and accurate output frequency the VCO is enclosed in a feedback loop, where the output frequency is divided down and compared to a much lower frequency reference clock typically produced by a crystal oscillator. The loop locks the divided down VCO output to the reference frequency, resulting a stable output frequency that is an integer (N) multiple of the reference frequency.
A linear or harmonic type VCO includes a varactor whose capacitance is responsive to the input control voltage, and is used to change the capacitance in an inductor-capacitor (LC) tank circuit or crystal resonator. A delay-based ring VCO operates using gain stages connected in a ring, with the output frequency being a function of the delay in each of stages.
Another type of frequency multiplier is the digital PLL, which operates in much the same manner as a PLL, except that the VCO is replaced by a digitally controlled oscillator (DCO) that runs at the required clock frequency, or some multiple, in response to digital input control signals supplied by a digital phase frequency detector. Still another frequency multiplier is a delay-locked loop (DLL), which has a controlled delay line that is voltage or digitally controlled. The DLL generates a plurality of phase shifted versions of the reference clock that are combined to produce a new clock signal that is a multiple of the reference frequency.
The most common type of reference source is a crystal oscillator, which relies upon the inherent stability of quartz crystal to provide a reference frequency that remains constant within a few parts per million. Microelectromechanical system (MEMS) resonators are small electromechanical structures that vibrate at high frequencies. For frequency and timing references, MEMS resonators are attached to sustaining amplifiers, to drive them in continuous motion and produce output reference signals. MEMS oscillators can be fabricated as multi-pin integrated circuits (ICs) to supply multiple signal phases.
The sampling clock for an analog-to-digital converter (ADC) is often generated using a PLL. Typically, the jitter of the sampling clock is dominated by the close-in phase noise of the PLL, especially when a ring oscillator type VCO is used. The clock jitter is one of the main limitations to the ADC signal-to-noise ratio (SNR) when sampling a high-frequency input signal. A crystal oscillator can provide a reference signal with a minimum of phase noise, but the available frequencies are too low for many applications.
One limitation, especially when the ratio of the output frequency to the reference frequency is large, is that the VCO must run many cycles between the generation of any correction information from phase comparisons with the reference signal, which occurs only once in the reference period. Between the feedback pulses (control signals to the VCO) at the rate of the reference frequency, the output phase can drift due to device noise or some external disturbance. To keep the feedback loop stable, the amount of correction that can be applied at a single reference period is also limited by the bandwidth of the loop-filter, which further delays the phase error correction. As a result, there is a limit to how much of the VCO phase noise the feedback loop can correct.
It would be advantageous if a method existed that provided an improvement in the phase noise correction possible in a system using phase-locked system clock.